The present invention relates generally to semiconductor device processing and, more particularly, to a method for forming robust solder interconnect structures by reducing effects of seed layer underetching with respect to a barrier layer.
In the manufacture of semiconductor devices, C4 (Controlled-Collapse Chip Connection) is a means of connecting integrated circuit chips to substrates in electronic packages. In particular, C4 is a flip-chip technology in which the interconnections are small solder balls (or bumps) formed on the chip surface. The top layers of an integrated circuit chip include various wiring levels, separated by insulating layers of dielectric material, that provide input/output for the device. In C4 structures, the chip wiring is terminated by a plurality of metal films that form the ball-limiting metallurgy (BLM). The BLM defines the size of the solder bump after reflow, and provides a surface that is wettable by the solder and that reacts with the solder material to provide good adhesion and acceptable reliability under mechanical and thermal stress. In addition, the BLM also serves as a diffusion barrier between the integrated circuit device and the metals in the interconnection.
As is known in the art, the BLM includes a continuous stack of metal films across formed over the wafer to be bumped. This stack of films, also known as a “seed layer” performs a dual function. First, the seed layer provides a conductive path for current flow during subsequent electrolytic deposition of the solder bumps. Second, portion of the original seed layer remains under the solder bumps and forms the basis for the BLM of the C4s. Accordingly, the seed layer must include at least one layer that is conductive enough to permit uniform electrodeposition across the entire expanse of the wafer. Moreover, the bottom layer must adhere well to the underlying semiconductor device passivation, while the top layer must interact sufficiently with the solder to form a reliable bond.
While different seed layer metallurgies are available in C4 fabrication, one common combination includes a sputtered titanium-tungsten (TiW) adhesion layer, followed by phased or codeposited chromium-copper (CrCu) and copper (Cu) layers. Once the seed layer is formed over the via-patterned passivation layer, another photolithographic patterning process is implemented for forming the solder material within the mask holes in which the C4 bumps are to be defined. In order to reduce the effects of dissolution of copper within the solder material after an extended number of reflow operations, a thin nickel/copper (Ni/Cu) layer is also commonly used in the BLM as a barrier therebetween. The Ni/Cu barrier layer is electroplated onto the portions of the seed layer left exposed following the C4 patterning step.
After the nickel/copper and solder bump materials are plated, the developed resist is removed and the remaining seed layer is removed by etching. More specifically, the Cu and CrCu layers are removed by electroetching, while the TiW layer is removed by a wet chemical etch process. Unfortunately, during the electroetching process, there is an undercut of the Cu and CrCu portions of the seed layer with respect to the Ni/Cu barrier layer. This results in an incomplete BLM in terms of the layers (TiW/CrCu/Cu/Ni) defined under the solder bump. In certain instances, about 30 to 40% of the outer edge of C4 base is left with an inadequate BLM stack. These defects are problematic in terms of the integrity of C4 joint reliability.
Accordingly, it would be desirable to implement a process of forming a BLM for C4 solder bump interconnects in a manner that does not result in a substantial underetch of the seed layer with respect to the barrier layer so as to adversely impact C4 structural integrity.